The present invention relates to data realignment in serial-to-parallel converters, and more particularly, to techniques for realigning the boundary between data bytes when converting serial data to parallel data.
A serial-to-parallel converter circuit is used to convert a serial data stream into a parallel data stream. Bits of data are shifted into a shift register from a single input data stream. The data bits stored in the register are then simultaneously shifted out of the register along parallel signal lines as parallel data Each data bit is output on a separate parallel signal line. The data bits are shifted out of the register as bytes of data (e.g., 8 bits each). Thus, the registers groups serial data bits into data bytes on parallel signal lines.
The register determines the boundary between one data byte and the next data byte. Typically, when serial data is converting to parallel data, the boundary between data bytes is determined randomly, depending upon when the data transmitting and receiving devices power up.
Therefore, it would be desirable to provide techniques to realign the boundary between output data bytes from a serial-to-parallel data converter to match a preset data boundary.